Central processing unit employing microprogrammable control for use in a data processing system
US3990052A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 25, 1974 |
| Grant date | Nov 2, 1976 |
| Priority date | — |
| Expiry date | Sep 25, 1994 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/262
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprogrammed processor having a versatile hardware and data path configuration in which control signals for data paths, the ALU function, the shifter and all other control signals are derived from the current microprogram control word which is normally periodically clocked into a ROM buffer. Included are capabilities for effective addressing, incrementing the program counter and computer instruction skips, all while the instruction register is being loaded from memory by direct connection of selected bits of the memory bus to the ROM buffer to derive a micro-instruction. Also included is a conditional skip condition allowing the processor to skip the next instruction by testing selected bits of the instruction register which manipulates the micro-code for this purpose. Another capability is that of hardware structuring to readily accommodate WCS. Other capabilities provide for bit and byte manipulation, allowing the micro-instruction to readily load constants into the ALU, and for marking purposes. Data path connections provide for selective connection of the register file and the ALU output to the memory bus dependent upon existing memory bus and data bus communication with t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.