Logic level decoding circuit
US3991379A · kind A · utility
19Cited by
3References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1975 |
| Grant date | Nov 9, 1976 |
| Priority date | — |
| Expiry date | Jun 3, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/20
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a digital system wherein digital data having two operating logic voltage levels corresponding to two different logic states is transmitted from one unit and received at another separate unit, circuitry is provided for determining the mean voltage value of the received logic voltage levels and for comparing the mean voltage value to the received data to provide decoding of the correct logic state of the individual signal bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.