Programmable latch and other circuits for logic arrays
US3993919A · kind A · utility
11Cited by
3References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1975 |
| Grant date | Nov 23, 1976 |
| Priority date | — |
| Expiry date | Jun 27, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This specification describes means that permit the variation of circuits, particularly latch circuits, used in programmable logic array chips (PLAs). The latch circuits are changeable to enable the selection of one of three different latch configurations to be used or in combination on the same PLA chip. The differences in the circuit configurations of the different types of latches occur only in metallization pattern of the chip so that chips with different latch configurations can be manufactured with a minimum of different processing steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.