Plasma display panel having integral addressing means
US3993921A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 23, 1974 |
| Grant date | Nov 23, 1976 |
| Priority date | — |
| Expiry date | Sep 23, 1994 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J11/12
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A plasma display panel incorporates a portion of the cell-addressing logic by associating with each row and column of a rectangular array a plurality of conductors which are selected by coded addressing signals. The coincidence or lack of coincidence of an appropriate pattern of such signals at each cell, as averaged by one or more conducting cover segments at each cell, selectively produces a potential suitable for initiating or extinguishing a gas discharge. A result of this structure is a reduction in the total number of, and complexity of, external drive circuits while retaining a direct write capability for each individual cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.