Enhancement-and depletion-type field effect transistors connected in parallel
US3995172A · kind A · utility
13Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1975 |
| Grant date | Nov 30, 1976 |
| Priority date | — |
| Expiry date | Jun 5, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit comprising the parallel connection of an enhancement-and a depletion-type FET which exhibits reduced power and improved performance for both logic as well as memory circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.