Processes of forming insulated gate field effect transistors with channel lengths of one micron in integrated circuits with component isolated and product
US3996655A · kind A · utility
22Cited by
1References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 25, 1975 |
| Grant date | Dec 14, 1976 |
| Priority date | — |
| Expiry date | Aug 25, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/761
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to methods of forming Insulated Gate Field Effect transistors and the product suitable for integrated circuits with channel lengths of 1 micron or less, the transistors being isolated from other transistors or other components in the circuit without the requirements of extra isolation steps. This is provided by means of a double diffusion which isolates the channel of the transistor from other elements in the circuit. Channel length is solely a function of the diffusion schedule through openings in the oxide through which the double diffusion takes place.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.