High speed divide-by-two circuit
US3997796A · kind A · utility
7Cited by
3References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 1975 |
| Grant date | Dec 14, 1976 |
| Priority date | — |
| Expiry date | May 14, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/2823
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed divide-by-two circuit operable in the 400 to 500 MHz frequency range comprising a pair of transistors having their emitters connected in common to an input circuit and their bases and collectors cross-coupled by a pair of capacitors. The collectors of the transistors are also coupled together by a single inductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.