Phase lock loop circuit
US4001713A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 15, 1976 |
| Grant date | Jan 4, 1977 |
| Priority date | — |
| Expiry date | Jan 15, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop circuit for a controlled oscillator employs a digital phase detector and maintains phase lock between trains of reference (R) pulses and controlled (C) pulses derived from the oscillator. Acquisition of a state of phase lock is aided by delaying or advancing the C-pulse relative to the next occurring R-pulse when the frequency of the C-pulses is higher or lower, respectively, than the R-pulse frequency. A frequency divider connected to the oscillator output is reset once during each cycle to produce C-pulses as an input to the phase detector and the R-pulse input to the phase detector is applied from a reference pulse source through a delay circuit. Logic elements responsive to the two phase detector inputs determine the relative frequencies of the latter and control operation of the frequency divider to either delay or advance the production of the C-pulse relative to the R-pulse without interrupting operation of the R-pulse source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.