Bucket-brigade delay line having reduced parasitic capacitances and method for making the same
US4002513A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 1975 |
| Grant date | Jan 11, 1977 |
| Priority date | — |
| Expiry date | Feb 25, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/895
Abstract
An MOS bucket brigade delay line having reduced parasitic capacitances and method for making the same, include a first set of diffused drain source regions in a semiconductor substrate, a thin gate oxide layer overlying said diffused regions, a plurality of gate electrodes having first and second edges, the first edge of each electrode substantially overlapping one of said diffused regions, each of these elements formed in conventional manner. A second set of diffused drain-source regions extends the first set of regions by an amount limited by the second edge of the gate electrodes. The second set of drain source regions is formed by utilizing the gate electrodes as a diffusion mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.