Complementary field effect transistor sense amplifier for one transistor per bit ram cell
US4003035A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 1975 |
| Grant date | Jan 11, 1977 |
| Priority date | — |
| Expiry date | Jul 3, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3562
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A random access memory includes a plurality of one-transistor storage cells. A plurality of sense-write conductors are included, each connected to a plurality of storage cells in a row of storage cells. A plurality of regenerative sense amplifiers are each coupled to two sense-write conductors. A one-transistor dummy storage cell is connected to each sense-write conductor. Read-write circuitry is coupled between a data conductor of the memory chip and one of the regenerative sense amplifiers for each of the rows, respectively. The dummy storage cell is selected whenever a storage cell on the opposite side of the regenerative sense amplifier is selected after redistribution of charge initially stored in the selected storage cell onto the sense-write conductor takes place. The sense voltage resulting from the charge redistributed on the opposite sense-write conductor is subsequently amplified by the sense amplifier, and provided in inverted and noninverted form on the two respective sense-write conductors. A CMOS transmission gate clocked by a first control signal and its logical complement balances the two sense-write conductors to precisely the same voltage. First and second clocke…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.