Multiplexer offset removal circuit
US4005273A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 8, 1976 |
| Grant date | Jan 25, 1977 |
| Priority date | — |
| Expiry date | Mar 8, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/10
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In a multi-channel multiplexed system, each signal-receiving input channel has a DC blocking capacitor. One of the input channels to the multiplexer is grounded making this channel a test channel. A signal-conditioner-and-amplifier network (SCAN) couples the multiplexer output to a utilization device. The spurious voltage developed across the capacitor in the test channel combined with the offset voltage across the SCAN will be substantially the same as each one of the spurious voltages developed across the capacitors in the other input channels in combination with the SCAN offset voltage. A sample-and-hold circuit consisting of a series capacitor and a normally ungrounded shunt switch is connected between the output of the SCAN and the input to the utilization device. Periodically, as during each scan cycle of the multiplexer, the capacitor in the sample-and-hold circuit will be charged to and hold a sample voltage having equal amplitude but opposite polarity to the spurious voltage developed across the test channel capacitor in combination with the SCAN.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.