Wafer scale integration system
US4007452A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 28, 1975 |
| Grant date | Feb 8, 1977 |
| Priority date | — |
| Expiry date | Jul 28, 1995 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for interconnecting a plurality of separate memories (on other circuits) on a wafer so as to electrically exclude defective memories and include operative memories. A single discretionary connection is associated with each of the separate memories and such connection is made (or broken) after a memory is tested. In addition to a bidirectional memory bus used for input/output data and addresses, the wafer includes a separate identity bus used to define the memory organization. The identity bus is interconnected by a plurality of incrementers, one associated with each memory. The signal on the identity bus is incremented by useable memories and such signal is compared to an address on the bidirectional memory bus to select memories in an organized manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.