Fault bypass for a processor associated scanner
US4009348A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 2, 1975 |
| Grant date | Feb 22, 1977 |
| Priority date | — |
| Expiry date | Jun 2, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q3/54591
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A processor equipment has an input highway connected to receive a multiplex signal from a number of peripheral devices such as multiplex units time division multiplxing telephone handsets. A counter is arranged to scan the devices for a processor interrupt signal and upon the occurrence of such a signal the counter is inhibited to enable the processor to take the appropriate action for the interrupting device, e.g. apply a dial tone. If one of the peripheral devices becomes faulty a store memorizes the fact that on a previous scan the device produced a non-valid interrupt signal and causes the address of a predetermined other peripheral device to be written into the counter at which scanning is to recommence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.