Filter with a reduced number of shift register taps
US4012628A · kind A · utility
9Cited by
4References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 15, 1975 |
| Grant date | Mar 15, 1977 |
| Priority date | — |
| Expiry date | Aug 15, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a discrete-time filter configuration employing a shift register having output taps at only preselected stages for developing an output signal that is responsive to the signal of each stage of a shift register. The desired output signal is computed in a filter processing network by multiplying each of the output taps signals by a plurality of filter coefficients, by appropriately delaying the multiplied signals and by summing the delayed signals to produce the desired output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.