High density CMOS process
US4013484A · kind A · utility
51Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 25, 1976 |
| Grant date | Mar 22, 1977 |
| Priority date | — |
| Expiry date | Feb 25, 1996 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/145
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating high density, high voltage CMOS devices. The process provides self-aligning, full channel stops which are formed prior to the fabrication of the active devices. The aligned full channel stops and a well are formed in the substrate without intermediate masking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.