Initial reset signal generator and low voltage detector
US4013902A · kind A · utility
37Cited by
9References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 6, 1975 |
| Grant date | Mar 22, 1977 |
| Priority date | — |
| Expiry date | Aug 6, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for generating an initial reset signal for a custom design CMOS digital system and for providing a diagnostic low voltage detect signal when the power supply voltage drops below a predetermined level. The circuit is fabricated with CMOS technology in conjunction with two external resistors and a diode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.