MIS-FETs isolated on common substrate
US4015281A · kind A · utility
21Cited by
6References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1971 |
| Grant date | Mar 29, 1977 |
| Priority date | — |
| Expiry date | Mar 5, 1991 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/765
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An enhancement-type and a depletion-type metal-insulator-semiconductor field effect transistor are formed on a common substrate of silicon and are electrically isolated from each other by a plurality of layers including, for example, a first layer of SiO.sub.2, a second layer of Al.sub.2 O.sub.3 capable of inducing holes in the surface portion of the substrate, and a third layer of SiO.sub.2, and the relation between the thicknesses of these layers is suitably selected for attaining the satisfactory isolation between these transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.