Timing circuit means
US4017746A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 1975 |
| Grant date | Apr 12, 1977 |
| Priority date | — |
| Expiry date | Jul 18, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/13
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A timing circuit is shown as employing a flip-flop for driving an output circuit portion as to have such output circuit portion in effect provide either a low or no output or a high output with such in turn being employed for turning on or turning off a related power circuit; a first high gain amplifier is employed as a means for placing the flip-flop into one of its states whenever an appropriate trigger signal is momentarily applied thereto, while a second high gain comparator amplifier is effective to provide a reset signal to the flip-flop whenever a particular span of time has elapsed from the application of the trigger signal; the timing for creating the reset signal is achieved as through an R-C network which provides, in effect, a threshold signal to the second amplifier upon the application of which the second amplifier produces the reset signal and applies it to the flip-flop thereby placing the output circuit portion in a condition wherein it has either a low or no output. Additional defeat or inhibiting means are provided to cause the output circuit portion to be placed in such a condition of either low or no output even if the timing phase of the overall cycle has not …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.