Standby apparatus for clock signal generators
US4019143A · kind A · utility
15Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 10, 1976 |
| Grant date | Apr 19, 1977 |
| Priority date | — |
| Expiry date | May 10, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0083
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A clock output signal is aligned in phase to conicide with the phase of signals derived from a master clock. In the event that there is a malfunction of the master, standby control circuitry modifies the phase of the clock output signal incremental quantities until it is in phase with the phase of signals from a standby clock. The clock output signal is thereafter maintained aligned in phase to coincide with the phase of the signals derived from the standby clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.