Interpolation-decimation circuit for increasing or decreasing digital sampling frequency
US4020332A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1975 |
| Grant date | Apr 26, 1977 |
| Priority date | — |
| Expiry date | Sep 24, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0685
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A general purpose interpolator-decimator circuit for increasing or decreasing the sampling rate of a digital signal by a factor L/M, where L and M are integers, is disclosed. The circuit includes means for determining each output sample by multiplying a sequence of previous input samples by a set of coefficients and accumulating the resulting products. L sets of coefficients, in which each coefficient is a function of the factors L and M, are stored in a specific sequence which permits sequential addressing of both the coefficients and input signal samples. A multistage decimator cascaded with a multistage interpolator to effect a narrow-band FIR filter is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.