Write speed-up circuit for integrated data memories
US4023148A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 1975 |
| Grant date | May 10, 1977 |
| Priority date | — |
| Expiry date | Nov 26, 1995 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/415
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Modern bipolar cross coupled memory cells for high density arrays use diodes as coupling elements from the cell to the bit lines. The write operation of these cells requires a high amount of current if the current gain of the cell transistors is high. The time required to perform a write operation is prolonged significantly due to the inherent capacitors in the cell known as the Miller effect. The described circuit completely eliminates the Miller effect during the write operation and makes the required write current completely independent of the current gain of the cell transistors. In the present invention this is accomplished by dropping the word line of such a cell from a stand-by potential to a select potential, so that the inner cell nodes are equally discharged, without disturbing the state of the cell, after which the word line is pulsed up to an intermediate potential between the select potential and the stand-by potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.