Priority interrupt handling system
US4024503A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1974 |
| Grant date | May 17, 1977 |
| Priority date | — |
| Expiry date | Mar 26, 1994 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/268
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer for executing a program made up of a plurality of instructions stored in an operational memory, in which the system is controlled by a set of microprograms stored in a read-only memory, the program instructions to be executed are transferred one at a time to a scratch pad memory, where they are used to address corresponding microprograms in the read-only memory. The microinstructions of the addressed microprogram are transferred one at a time to a microinstruction register, where each one is used to control the generation of a plurality of sets of commands to various components of the machine for executing the program instruction. The control unit includes means for transmitting control signals and data to the peripheral units with the data being already decoded into a form in which it is able to directly control the data output mechanism of the peripheral unit, without further modifications by a peripheral unit control unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.