Decoder structure for a folded logic array
US4025799A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1975 |
| Grant date | May 24, 1977 |
| Priority date | — |
| Expiry date | Nov 6, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018507
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This specification describes a decoder for use in a programmable logic array (PLA) of the type having opposite ends of input lines of the array connected to outputs of different decoders. Instead of using the outputs of two two-bit decoders to drive four input lines, as was previously done, four one-bit decoders are used to drive the four input lines. This arrangement permits the one-bit decoders with minor modifications to be used to perform four one-bit decodes of four input signals, two two-bit decodes on two sets of two input signals on either side of the array and one two-bit decode on two input signals that are on opposite sides of the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.