Open loop digital frequency multiplier
US4025866A · kind A · utility
12Cited by
5References
6Claims
0Family size
Inventors
Key dates
| Filing date | Nov 10, 1975 |
| Grant date | May 24, 1977 |
| Priority date | — |
| Expiry date | Nov 10, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An open loop digital frequency multiplier with a multiplied output synchonized to low frequency clock pulses. The system includes a multi-stage digital counter which provides a pulse output as a function of an integer divisor. The integer divisor and the timing or counting cycle of the counter are interrelated to the frequency of a clock input. The counting cycle is controlled by a one-shot multivibrator which, in turn, is driven by a reference frequency input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.