Sense circuit for memory storage system
US4027176A · kind A · utility
17Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 1975 |
| Grant date | May 31, 1977 |
| Priority date | — |
| Expiry date | Nov 26, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This teaches a sense circuit for an integrated memory storage system in which the storage cell output is detected by a differential amplifier, controlling a flip-flop, serving as a latch, having load elements which also function as the load elements of the latch to ensure an optimum power and speed product. The latch can be coupled to an output driver circuit through a current switch which shares common elements with the latch to assure that the latch remains symmetrical even when used with an output driver having asymmetrical control.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.