Control circuit with time delay
US4027221A · kind A · utility
2Cited by
8References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 11, 1975 |
| Grant date | May 31, 1977 |
| Priority date | — |
| Expiry date | Feb 11, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H7/08
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A control circuit, such as a motor control circuit, includes a capacitance connected at one side with a timing resistance to the gate of a field effect transistor (FET) which inhibits energization of a load, such as a motor. The FED controls a semiconductor switch which is connected by a diode to the other side of the capacitance to prevent reactuation of the circuit during a time delay determined by the rate of current flow through a timing resistance to the one side of the capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.