Peripherals interrupt control unit
US4027290A · kind A · utility
10Cited by
17References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1974 |
| Grant date | May 31, 1977 |
| Priority date | — |
| Expiry date | Jun 7, 1994 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple control unit for selectively connecting a plurality of peripheral units to a central processor comprising a register for storing the interruptions coming from the peripherals; a disabling circuit for disabling the cell storing the interruption executed by the central processor in response to an end-of processing signal generated from the CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.