Digital computer arrangement for high speed memory access
US4028663A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1974 |
| Grant date | Jun 7, 1977 |
| Priority date | — |
| Expiry date | Jun 5, 1994 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing arrangement is disclosed including a central processing unit, a plurality of peripheral units coupled to a peripheral bus, a memory access controller, a first memory bus, and a second memory bus. The first memory bus serves a first plurality of memory units and the second memory bus serves a second plurality of memory units. The memory access controller selects which of the peripheral units may use the peripheral bus to access a memory bus during a particular time interval. If use of a particular memory bus is requested by a peripheral unit for an interval in which that memory bus is required by the central processing unit, the memory access controller preempts the usage of that memory bus by the peripheral unit for the interval. In addition, when a peripheral unit which has been permitted to use the peripheral bus is preempted from actually communicating with a memory in a particular interval, the memory access controller operates in combination with the peripheral units to maintain the priority of the preempted peripheral unit for requesting use of the peripheral bus during the next possible interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.