Method and apparatus for refreshing semiconductor memories in multi-port and multi-module memory system
US4028675A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 1973 |
| Grant date | Jun 7, 1977 |
| Priority date | — |
| Expiry date | May 14, 1993 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4234
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-module, multi-port memory system includes modules having semiconductor memory circuits which require periodic refreshing to retain the contents stored therein. Priority circuits resolve conflicts between the multi-port access of the memory modules and the refreshing requirements of semiconductor memory circuits within the modules. The modules of the preferred embodiment are arranged in a polymorphous array of selectably expendable rows and columns. Modules utilizing different memory technologies may be combined within the address space of the array without interfering with independent multi-port access by various computer processors and other memory using devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.