Digital double differential phase-locked loop
US4030045A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 6, 1976 |
| Grant date | Jun 14, 1977 |
| Priority date | — |
| Expiry date | Jul 6, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/235
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A first generator provides a reference pulse train having a predetermined reference frequency. A second generator including a voltage controlled oscillator provides a bit clock having a repetition frequency locked to the repetition frequency of the bits of digital data. A first divider coupled to the first generator divides the reference frequency by a selected one of a first division factor and a second division factor different than the first division factor. A fourth divider coupled to the second generator divides the repetition frequency of the bit clock by a selected one of a third division factor and a fourth division factor different than the first, second and third division factors. A phase comparator coupled to the first and second dividers compare the phase of the output signals of the first and second dividers and produces a control signal proportional to the phase difference between the output signals of the first and second dividers. The control signal is coupled through a loop filter to the voltage controlled oscillator to lock the phase of the bit clock to the bits of the digital data. Logic circuitry coupled to the digital data source, the second generator and the f…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.