Addressing system in an information processor
US4031514A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 2, 1975 |
| Grant date | Jun 21, 1977 |
| Priority date | — |
| Expiry date | Sep 2, 1995 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/355
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An addressing system in an information processor for accessing to data regularly scattered in the whole memory region, comprising an index register, an adder, an address register, an instruction register, and a circuit which detects information of a portion of an operation part of the instruction register. When the detection output of the detecting circuit is specified information, information of an address part of the instruction register and information of the index register are added by the adder. The result is stored into the address register. After designating an address, the added information is shifted to the index register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.