Process for producing semiconductor memory device utilizing selective diffusion of the polycrystalline silicon electrodes
US4031608A · kind A · utility
12Cited by
10References
20Claims
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Key dates
| Filing date | Apr 8, 1976 |
| Grant date | Jun 28, 1977 |
| Priority date | — |
| Expiry date | Apr 8, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device provided with one transferring electrode, one gate electrode and one diode of a charge coupled device is produced by a process with a reduced number of steps of diffusion and patterning. Both electrodes consist of doped polycrystalline silicon and both are electrically connected to a resistive layer which consists of non-doped polycrystalline silicon. A potential barrier between the region of both electrodes is removed due to the resistive layer. The resistive layer is formed by utilization of a two stage deposition of the polycrystalline silicon layer with appropriate masking steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.