Logic array with enhanced flexibility
US4032894A · kind A · utility
40Cited by
1References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 1, 1976 |
| Grant date | Jun 28, 1977 |
| Priority date | — |
| Expiry date | Jun 1, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17716
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A single-chip programmable logic array (PLA) in which the AND (search) array outputs are coupled to the OR (readout) array through a NOT array of selectable on-chip inverters. Provision is also made for selectable interconnection of inverted or non-inverted NOT array outputs to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.