Integrated circuit fusing technique
US4032949A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 18, 1976 |
| Grant date | Jun 28, 1977 |
| Priority date | — |
| Expiry date | Oct 18, 1996 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/926
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fusing technique whereby a fuse is fabricated upon a substrate by integrated circuit techniques. Three or more layers of chemically dissimilar metals are depositedupon the region where the fuse is to be formed. The top layers are then etched away from the region where the fusible link is to be formed leaving the lower two layers, the top one of which forms the actual fusible link. The lower layer is then etched away leaving the fusible link suspended from the underlying substrate. The current necessary to cause such a fuse to blow is consistent from fuse to fuse since the physical dimensions of the fusible link can accurately be controlled with the integrated circuit techniques used and, since the fusible link is not in contact with the substrate, the rate at which heat is conducted away from the fusible link cannot vary from fuse to fuse. The method is used to advantage in microwave power and oscillator diode circuits such as those used in phasedarray radar systems and in read only memories and memory reconfiguration applications, as well as other semiconductor fusing applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.