High density semiconductor integrated circuit layout
US4032962A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1975 |
| Grant date | Jun 28, 1977 |
| Priority date | — |
| Expiry date | Dec 29, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor in a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction. For the most part, this conductor connects the second device with one of the conductors in the first set. The reference potential connections to each circuit are also made preferably by conductive channels running in the same direction. With respec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.