Parity predict network for M-level N'th power galois arithmetic gate
US4035626A · kind A · utility
4Cited by
6References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 29, 1976 |
| Grant date | Jul 12, 1977 |
| Priority date | — |
| Expiry date | Mar 29, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/13
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parity predict circuit for an M-level N'th power Galois arithmetic gate using binary logic elements and a method of the designing thereof is disclosed. The method involves an algorithm that the logic designer utilizes to visually analyze the output of the arithmetic gate using a heuristic technique to determine the procedure for intercoupling the outputs of the gate's 1 through m-1 levels of parity trees as inputs to the parity predict parity tree. This visual analysis obviates the laborious mathematical treatment of the arithmetic gate priorly utilized to design a parity predict network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.