Supervisor address key control system
US4035779A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1976 |
| Grant date | Jul 12, 1977 |
| Priority date | — |
| Expiry date | Apr 30, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1458
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System mode controls for obtaining limited addressability for supervisor programming operations without disturbing a user address key currently contained in a user key register (UKR). The mode controls are provided by bits in a system register called a level status register (LSR), which include an APM bit, and a supervisor state bit. The largest supervisor addressability is obtained when both the APM and supervisor state bits are set on, which permits execution of a supervisor program which can access user data and programs. In more detail, each instruction fetch must be in the supervisor key area, identified by a predetermined supervisor key value which is not in the UKR, while each operand of the fetched supervisor instruction is accessed in the user key area identified by the current key in the UKR. The supervisor is not permitted to access any user area which does not have its key in the UKR. Thus, the supervisor can be prevented from having addressability over part or all of the main memory. However, if the APM bit is off while the supervisor bit is on, all instruction and operand storage accesses can only be made in the supervisor key area, regardless of whether the superviso…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.