Computer-peripheral interface
US4037210A · kind A · utility
7Cited by
6References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 29, 1976 |
| Grant date | Jul 19, 1977 |
| Priority date | — |
| Expiry date | Jan 29, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a computer system utilizing an interface unit for routing the information exchanged between processor units and memory units, in a temporal multiplex manner whereby the exclusive access of any one processor to any memory proceeds concurrently with the exclusive access of another processor to another memory. The system includes at least two independently operable processors and at least two independently addressable and separately operable memories, the latter being connected to the former through the interface unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.