Methods for making transistor structures
US4037307A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 3, 1976 |
| Grant date | Jul 26, 1977 |
| Priority date | — |
| Expiry date | Nov 3, 1996 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an extremely short channel FET is made by forming a metal layer over a wafer, depositing silicon dioxide over part of the metal layer, oxidizing the exposed metal, controllably etching a portion of the silicon dioxide to expose a small strip of the nonoxidized metal layer, electroplating the exposed metal strip, thereby to form an extremely narrow gate electrode, removing the deposited SiO.sub.2, the metal oxide and the remaining metal layer to leave only the gate electrode, and using the gate electrode as a mask for ion implanting source and drain regions. Since the gate electrode can be made so narrow, the channel region is correspondingly short to give extremely high frequency capabilities. Other embodiments are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.