Circuit arrangement for a quartz controlled electrical clock
US4037402A · kind A · utility
1Cited by
9References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 12, 1975 |
| Grant date | Jul 26, 1977 |
| Priority date | — |
| Expiry date | Mar 12, 1995 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG04C13/105
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit arrangement for a quartz controlled electrical clock comprising an oscillator stage a frequency divider separated from the oscillator stage by a gate controlled by a control logic unit, an output stage connected to the frequency divider and a stepping motor connected to the output stage, the control logic unit responding to a command signal to open the gate and disconnect the oscillator stage from the frequency divider with the frequency divider retaining its memory content at the instant of disconnection and with no current flowing through the drive coils of the stepping motor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.