Multiplier circuit
US4038566A · kind A · utility
3Cited by
3References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 22, 1976 |
| Grant date | Jul 26, 1977 |
| Priority date | — |
| Expiry date | Mar 22, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G1/0005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gain control or multiplier circuit in which an ac signal is applied through bipolar diodes having logarithmic response characteristics to the bases of bipolar transistors connected in series and having an output at their junction, the diodes being directly cross connected to the bases, and gain control signals of opposite polarities being applied to the bases, thereby providing a linear output from the transistors despite their non-linear response characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.