Method and device for synchronizing the receiver clock in a data transmission system
US4039748A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 1976 |
| Grant date | Aug 2, 1977 |
| Priority date | — |
| Expiry date | Apr 8, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/046
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock setting circuit is provided at a receiving modem for adjusting the phase of a timing signal defining the signal sampling instants. The received signal is filtered in two filters to derive a first signal having a phase .phi..sub.1 and a frequency f.sub.1 equal to f.sub.c - 1/2T, f.sub.c being the carrier frequency and 1/T being the transmission baud rate, and a second signal having a phase .phi..sub.2 and a frequency f.sub.2 equal to f.sub.c + 1/2T. The first and second derived signals are combined to derive an error signal indicative of the phase difference .phi..sub.2 - .phi..sub.1 which difference is used for adjusting the phase of a phase locked oscillator which provides the timing signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.