Automatic phasing circuit to transfer digital data from an external interface circuit to an internal interface circuit
US4039960A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 1976 |
| Grant date | Aug 2, 1977 |
| Priority date | — |
| Expiry date | Jun 29, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The phasing circuit transfers digital data from an external interface circuit to an internal interface circuit with no bit errors and no violation of bit count integrity under control of an external clock having a given frequency and a given phase and an internal clock having a frequency equal to the given frequency and a phase that is different than the given phase. The phasing circuit includes a data output from the external interface circuit, a first clock output to couple the external clock from the external interface circuit, a data input to the internal interface circuit, at least a second clock output to couple the internal clock from the internal interface circuit, at least first and second D-type flip flops having their D inputs and Q outputs coupled in cascade with each other, the data output and the data input and logic circuitry coupled to the clock input of each of the first and second flip flops, the second clock output and a selected one of the data output and the first clock output to select the internal clock or an inverted version of the internal clock as the clock for the first flip flop to provide the desired digital data transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.