Complementary MOS logic circuit
US4040015A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 22, 1976 |
| Grant date | Aug 2, 1977 |
| Priority date | — |
| Expiry date | Jun 22, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/184
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic complementary metal -oxide-semiconductor circuit (CMOS) includes a pair of gate stages connected in cascade. The first gate stage includes a first logic block which effects a prescribed logical function, the logic block being connected between a P-type and the N-type MOSFET. The source electrodes of the P-type and the N-type MOSFETs are connected between a power supply and ground, respectively, and their gate electrodes are connected in common. Moreover, the first gate stage has its output terminal connected to a load capacitor. The second logic block is also connected between a P-type MOSFET and an N-type MOSFET. The source electrodes of these MOSFETs are connected between a power supply and ground, respectively, while the gate electrodes thereof are connected in common. Also, a second load capacitor is connected to the output of the second gate stage. A pair of pulse signals, inverted with respect to each other, are applied to the first and second gate stages for driving the same, respectively. One of the MOSFETs making up the second logic block is of the type and is connected so that, when the power supply voltage applied to the gate thereof from the first gate stage, …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.