Memory system with reduced block decoding
US4040029A · kind A · utility
10Cited by
11References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 21, 1976 |
| Grant date | Aug 2, 1977 |
| Priority date | — |
| Expiry date | May 21, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory module construction including separate internal block decoders and system for utilization. Some of the memory modules in a multi-module memory system include a block address decoder providing an external signal when the corresponding module is addressed. A gate, responsive to the external signals, enables the memory modules which do not include a block address decoder. If more than one memory module do not include a block address decoder, then certain address lines or special control lines, in conjunction with the gate, select which memory module is to be enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.