Buffer chaining
US4040037A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 1, 1976 |
| Grant date | Aug 2, 1977 |
| Priority date | — |
| Expiry date | Jun 1, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system allocation of excessive main/working storage space to sequential input records (input blocks) of indeterminate length frequently results in wasteful fragmentation. This is avoided by the present invention. An input-output channel of conventional construction is modified so that in chaining mode it (the channel) can operate optionally to: (1) transfer sequential input data blocks of unspecified length into contiguous positions in main storage, and (2) without CPU interruption/intervention store delimiting information, in storage locations containing Channel Command Words (CCW's) designating respective transfers, which effectively distinguishes storage boundaries between adjacent blocks. The storage of delimiting information effectively relieves the control and application programs of the central system of responsibility for analyzing the information context of the data in each block for "possibly obscure" delimiting intelligence. The foregoing routing and delimiting operations may be made entirely transparent to the peripheral attachment interface of the channel so that peripheral attachment is not complicated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.