Method of making a transistor device
US4040877A · kind A · utility
4Cited by
9References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 1976 |
| Grant date | Aug 9, 1977 |
| Priority date | — |
| Expiry date | Aug 24, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/78
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plurality of discrete transistor devices are produced on a semiconductor wafer and isolated from one another by moat etching. A passivation layer is then deposited in the moats separating the discrete transistor devices. The semiconductor wafer is then scribed and broken along lines delineated by the moats. The disclosed method permits testing of each discrete transistor device prior to separation from the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.