Signal processing devices using residue class arithmetic
US4041284A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 7, 1976 |
| Grant date | Aug 9, 1977 |
| Priority date | — |
| Expiry date | Sep 7, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/729
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for performing arithmetical calculations on a plurality, N, of ital input signals, utilizing residue class arithmetic, comprising a plurality N of means for coding the N input digital signals into digital modulo m.sub.i integers, K.ltoreq.i.gtoreq.1. K may have a value of approximately 4. A plurality N of means, each means having an input connected to each coding means, converts the digital modulo m.sub.i integers into corresponding analog modulo m.sub.i signals. A plurality N of means performs a mathematical operation on the analog modulo m.sub.i integers, each means having an input connected to a D/A converting means. The means may be a multiplier or a correlator. A plurality N of means, connected to the N operation means, converts the analog modulo m.sub.i integers from the operation means into digital modulo m.sub.i integers. Means, connected to the N A/D converting means, decodes the digital modulo m.sub.i numbers into digital binary outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.