High-speed digital multiply-by-device
US4041296A · kind A · utility
2Cited by
5References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1975 |
| Grant date | Aug 9, 1977 |
| Priority date | — |
| Expiry date | Dec 3, 1995 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/523
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
High speed digital multiply-by-three device comprising a sum generation unit associated with a carry look-ahead unit, the latter comprising means for generating the carry bit C.sub.k.sub.+1 to be fed to the (k+1).sup.th stage of said sum generation unit by performing the logic function EQU C.sub.k.sub.+1 =X.sub.k.sup.. X.sub.k.sub.-1 +(X.sub.k.sub.-1.sup.. X.sub.K.sub.-2 + . . . + X.sub.k.sub.-1.sup.. X.sub.k.sub.-3.sup.. X.sub.k.sub.-5 . . . X.sub.1) + (X.sub.k.sup.. X.sub.k.sub.-2.sup.. X.sub.k.sub.-3 + . . . + X.sub.k.sup.. X.sub.k.sub.-2.sup.. X.sub.k.sub.-4 . . . X.sub.0)
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.