Multi-processor data processing system peripheral equipment access units
US4041460A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 1976 |
| Grant date | Aug 9, 1977 |
| Priority date | — |
| Expiry date | May 17, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each store and peripheral unit in system 250 is connected to the processor buses and includes an interface access-unit which makes each device appear the same to the or each processor. Essentially each access-unit includes a module-address register, a data-in register and/or a data-out register, a status register and a command register. The module-address register is used to receive and store the address received by the access-unit when addressed by an interrogating processor. The module address register is addressable by an interrogating processor using one of two "addresses". One address causes the contents of the module address register to be returned to the interrogating processor while the other "address" causes the inverse of the contents of the module address to be returned to the interrogating processor. This arrangement makes it possible to completely check a processor bus using only two transactions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.